`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2022/10/29 21:45:38
// Design Name: 
// Module Name: mod_s2p
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module mod_s2p(
    clk_s,
    clk_p,
    rst,
    zc_rom_ena,
    restart,
    rom_addr,
    data_s,
    data_p,
    cnt_2048
    );
 input clk_s;
 input clk_p;
 input rst;
 input zc_rom_ena;
 input restart;
 input [12:0] rom_addr;
 input data_s;
 output reg [3:0] data_p;
 output reg [10:0] cnt_2048 ;

 reg [3:0] temp;
 reg [1:0] cnt;
 reg din1;
 reg din2;
 reg din3;
 always@(posedge clk_s)begin
     if(rst||restart)begin
         din1 <= 1'd0;
         din2 <= 1'd0;
         din3 <= 1'd0;
     end
     else begin
         //if(cnt[0])begin
             din1 <= data_s;
             din2 <= din1;
             din3 <= din2;
        // end
     end
 end
 
 always@(posedge clk_s)begin
     if(rst||restart)begin
         data_p <= 4'd0;
         cnt <= 2'd0;
         cnt_2048 <= 10'd0;
     end
     else if(restart)begin
         cnt <= 2'd0;
     end
     
     else begin
         cnt <= cnt + 1'd1;
         if(rom_addr == 13'd1)begin
             cnt_2048 <= 11'd2047;
         end
         
         if(cnt == 2'd0)begin
             data_p <= {din3,din2,din1,data_s};
             cnt_2048 <= cnt_2048 + 1'd1;
         end
     end
 end
 
endmodule

